The present invention relates to a fault correction apparatus, and more particularly to a fault correction apparatus for correcting data read out from an address array of a store-in cache memory.
In a store-in (also called a "write-back" or a "copyback") cache memory, information is written only to a block in the cache memory. A modified cache block is written to main memory (this is called a "write-back") only when it is replaced on a cache miss (this is called a "replacement").
In the replacement, a data fault in the address array may cause misjudgment as to whether the block should be written to a main memory. If it is judged incorrectly that the block of the cache memory is unmodified even though the block has been modified, then the irreplaceable modified information is lost. To avoid such a problem, the reliability of the address array must be improved.
From a reliability point of view, a fault may be corrected with an error correction code before determination of a cache "hit"/"miss". However, in such a technique, the fault correction process is a critical path in determining a machine cycle so that the processing speed is decreased.
In the conventional store-in cache described above, it is difficult to determine a cache hit/miss in one machine cycle when a fault is detected in data read-out from the address array. Therefore, the entire system processing is stopped by the system checking when such a fault is detected. This approach inevitably deteriorates the system reliability. On the other hand, if a cache index is processed after correction of a fault, a machine cycle is extended by increasing delay time, so that processing performance deteriorates.